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2020 IEEE/ACM ICCAD CAD Contest — Call for Participation

The CAD Contest at ICCAD (http://iccad-contest.org/2020/) is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of Electronic Design Automation (EDA). It is open to multi-person teams world-wide. Each year the organizing committee announce three challenging problems in different topic areas provided by industrial companies. Contestants can participate in one or more problems. The prizes will be awarded at an ICCAD special session dedicated to this contest.

Since its inaugural year of 2012, the CAD Contest at ICCAD has been attracting more than a hundred teams per year, fostering productive industry-academia collaborations, and leading to hundreds of publications in top-tier conferences and journals. The contest undoubtedly boosts EDA research and keeps enhancing its impact.

Contest Problems:
Problem A — X-value Equivalence Checking 
Problem B — Routing with Cell Movement 
Problem C — GPU Accelerated Logic Re-simulation 

Timeline & Schedule:
Feb. 1 —  Contest starts!
May 8 — Registration ends.
Jun. 14 —Alpha test submission
Jul. 19 — Beta test submission
Aug. 23 — Final test submission
Nov. 2 — Award ceremony at ICCAD

Contest Chair:
Ing-Chao Lin; National Cheng Kung Univ.

Contest Co-chairs:
Ulf Schlichtmann; Technical University of Munich
Tsung-Wei Huang; University of Utah
Mark Po-Hung Lin; National Chiao Tung University

Topic Chairs:
Jacky (Chih-Jen) Hsu, Rocky (Chi-An) Wu, and Ching-Yi Huang;  Cadence Design Systems, Inc.
Kai-Shun Hu and Ming-Jen Yang;  Synopsys, Inc.
Yanqing Zhang, Haoxing Ren, and Brucek Khailany;  Nvidia Corp.
 

Sponsors:
IEEE CEDA (http://ieee-ceda.org/)
ACM SIGDA (http://sigda.org/)
Ministry of Education, Taiwan (http://www.edu.tw/)
Synopsys, Inc.(http://www.synopsys.com/)
Cadence Academic Network (http://www.cadence.com/)
Taiwan IC Design Society (http://www.ticd.org.tw/)
Nvidia (https://www.nvidia.com/en-us/)
National Chip Implementation Center, Taiwan (http://www.cic.narl.org.tw/)

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2020 IEEE/ACM ICCAD CAD Contest — Final Call for Participation & Extended Deadline to May 15

The CAD Contest at ICCAD (http://iccad-contest.org/2020/) is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of Electronic Design Automation (EDA). It is open to multi-person teams world-wide. Each year the organizing committee announce three challenging problems in different topic areas provided by industrial companies. Contestants can participate in one or more problems. The prizes will be awarded at an ICCAD special session dedicated to this contest.

Since its inaugural year of 2012, the CAD Contest at ICCAD has been attracting more than a hundred teams per year, fostering productive industry-academia collaborations, and leading to hundreds of publications in top-tier conferences and journals. The contest undoubtedly boosts EDA research and keeps enhancing its impact.

Contest Problems:

Problem A — X-value Equivalence Checking (Cadence Design Systems, Inc.)
Problem B — Routing with Cell Movement (Synopsys, Inc.)
Problem C — GPU Accelerated Logic Re-simulation* (Nvidia Corp.)

*Amazon GPU credits will be provided to participating teams.

Timeline & Schedule:

May 15: Registration ends

June 14: Alpha test submission
July 19:  Beta test submission
Aug. 23: Final test submission
Nov. 2: Award ceremony at ICCAD

Contest Chair:
Ing-Chao Lin (National Cheng Kung Univ.)

Contest Co-chairs:
Ulf Schlichtmann (Technical University of Munich)
Tsung-Wei Huang (University of Utah)
Mark Po-Hung Lin (National Chiao Tung University)

Topic Chairs:
Jacky (Chih-Jen) Hsu, Rocky (Chi-An) Wu, and Ching-Yi Huang (Cadence Design Systems, Inc.)
Kai-Shun Hu and Ming-Jen Yang (Synopsys, Inc.)
Yanqing Zhang, Haoxing Ren, and Brucek Khailany (Nvidia Corp.)

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Programming Contest: Machine Learning + Logic Synthesis

29th International Workshop on Logic & Synthesis

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The International Workshop on Logic and Synthesis (IWLS) organizes annual programming contest in the areas of logic synthesis, optimization, and verification of integrated circuits and systems. Participants from both academia and industry are welcome to submit their programming solutions to a challenging programming problem. Team participations are encouraged. The winners will be recognized at the IWLS Workshop, co-located with the Design Automation Conference this year.

This year’s topic is at the intersection of machine learning and logic synthesis. The participants are asked to write a program to learn an unknown Boolean function from a training set consisting of input-output pairs. The goal is to maximize the test accuracies on a set of hidden tests. Details of the contest can be found at: http://www.iwls.org/iwls2020/ (Programming Contest Section).

This year’s contest is contributed by Alan Mishchenko (UC Berkeley) and Satrajit Chatterjee (Google AI).

Submission deadline: June 12, 2020

Please contact iwls.contest.2020@gmail.com for questions.

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SRC@ICCAD

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SRC@ICCAD

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WOSET 2020
Third Workshop on Open-Source EDA Technology

Co-located with ICCAD 2020, November 5. WOSET will now be a virtual workshop and may expand to more than a single day to accommodate time zones. There will be no registration cost to attend!

The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that overview existing or under-development open-source tools, designs and technology libraries. A live demo session for tools in advanced state will be planned. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools. A cash award will be given for a Best Tool Award.

Submissions (2-4 pages):
Overview of an existing or under-development open-source EDA tool.
Overview of support infrastructure (e.g. EDA databases and design benchmarks).
Open-source cloud-based EDA tools
Position statements (e.g. critical gaps, blockers/obstacles)
Prizes:

WOSET will award $850 in prizes to the top open-source contributions.

Important dates:
Sept 6th 2020: submission due date.
Sept 15th 2020: notification due date.

Submission Information:
https://woset2020.hotcrp.com/
Please submit 2-4 page (US Letter) papers using the IEEE Conference Template

For inquiries, please contact Matthew Guthaus (mrg@ucsc.edu) or Jose Renau (renau@ucsc.edu).

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Call for Papers ASP-DAC 2021

26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021) Date : Jan.18-21, 2021

Place: Miraikan (The National Museum of Emerging Science and Innovation), Tokyo, Japan http://www.aspdac.com/

Important Dates:

Deadline for submission: July 26 (Sun), 2020, 5 PM AOE (Anywhere on earth)
Notification of acceptance: Sep. 13 (Sun), 2020
Deadline for final version: Nov.  6 (Fri), 2020, 5 PM AOE (Anywhere on earth)

For detailed instructions for submission, please refer to the "Authors'' Guide" at:

http://www.aspdac.com/

Contacts:

Conference Secretariat: aspdac2021@aspdac.com
TPC Secretariat: aspdac2021-tpc@aspdac.com

Aims of the Conference:

ASP-DAC 2021 is the 26th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.

In light of the continued Covid-19 pandemic situation, the format of the conference is subject to future change.  The options include fully in-person conference, hybrid conference (in person plus live video presentation) and fully virtual conferences. All papers presented, whether in-person or online, will be published. Please check the ASP-DAC 2021 website for updates.

Areas of Interest:

Original papers in, but not limited to, the following areas are invited.

 1. System-Level Modeling and Design Methodology:

 2. Embedded Systems and Cyberphysical Systems:

 3. Embedded Systems Software:

 4. Memory Architecture and Near/In Memory Computing:

 5. AI/Machine Learning System Designs:

 6. Photonic/RF/Analog-Mixed Signal Design:

 7. Approximate, Bio-Inspired and Neuromorphic Computing:

 8. Logic/High-Level Synthesis and Optimization:

 9. Physical Design:

10. Design for Manufacturability and Reliability:

11. Design and Analysis for Timing and Low Power:

12. Testing, Validation, Simulation, and Verification:

13. Hardware and Embedded Security:

14. Emerging Devices, Technologies and Applications:

Please note that each paper shall be accompanied by at least one different conference registration at the speaker''s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals.

Panels, Special Sessions and Tutorials:

Suggestions and proposals are welcome and have to be addressed to the Conference Secretariat

(e-mail: aspdac2021@aspdac.com) no later than August 2 (Sun), 2020.

Sponsors:

ACM SIGDA, IEEE CASS, IEEE CEDA, IEICE ESS, IPSJ SIGSLDM

ASP-DAC2021 Chairs:

General Chair: Toshihiro Hattori (Renesas Electronics Corporation)
Technical Program Chair: Sheldon Tan (University of California, Riverside)
Technical Program Vice Chair: Masanori Hashimoto (Osaka University, Japan) 

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Call for Designs : University LSI Design Contest @ ASP-DAC 2021

Date : Jan.18-21, 2021

Place: Miraikan (The National Museum of Emerging Science and Innovation), Tokyo, Japan http://www.aspdac.com/

Important Dates:

Deadline for summary: July 26 (Sun), 2020, 5 PM AOE (Anywhere on earth)
Notification of acceptance: Sep. 13 (Sun), 2020
Deadline for camera-ready : Nov.  6 (Fri), 2020, 5 PM AOE (Anywhere on earth)

Contact Email: aspdac2021-udc@aspdac.com

Aims of the Contest:

As a unique feature of ASP-DAC 2021, the University LSI Design Contest will be held. The aim of the Contest is to encourage education and research on VLSI design at universities and other educational organizations. We solicit designs that fit in one or more of the following categories:

  (1) Designed, and actually implemented on chips in universities or other educational

      organizations during the last two years;

  (2) Designs that report actual measurements from implementations;

  (3) Innovative design prototypes.

Interesting or excellent designs selected will be honored by providing the opportunities for presentation in a special session at the conference. Award(s) will be given to a few numbers of outstanding designs, selected from those presented at the conference.

Areas of Design:

Application areas or types of circuits of the original LSI circuit designs include (but are not limited to):

  (1) Analog, RF and Mixed-Signal Circuits, (2) Digital Signal Processing, (3) Microprocessors,

  (4) Custom ASIC.

Methods or technology used for implementation include:

  (a) Custom ASIC and Cell-Based LSIs, (b) Gate Arrays, (c) FPGA/PLDs.

Submission of Design Descriptions:

A camera-ready summary is requested to be prepared within 2 pages including figures, tables, and references. It is strongly recommended that measured experimental results and a chip micrograph are included in the summary. Specification of the submission format will be available at http://www.aspdac.com/ Please note that each paper shall be accompanied by at least one different conference registration at the speaker''s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. Please do not submit the same paper as a regular paper.

Review:

Submitted designs will be reviewed by the Design Contest Committee in a process similar to the review process for the technical papers. The following criteria will be applied in the selection of designs:

  (1) Reliability of design and implementation, (2) Quality of implementation,

  (3) Performance of the design, (4) Novelty of application, algorithm, architecture,

  (5) Others.

Interesting or excellent designs selected will be presented at a special session of the conference.

Presentation:

An author of each selected design will be required to make a short presentation at a special session of ASP-DAC 2021. A digest of each design to be presented will be included in the conference proceedings.

In light of the continued Covid-19 pandemic situation, the format of the conference is subject to future change. The options include fully in-person conference, hybrid conference (in person plus live video presentation) and fully virtual conferences. All papers presented, whether in-person or online, will be published. Please check the ASP-DAC 2021 website for updates.

ASP-DAC2021 Chairs:

General Chair: Toshihiro Hattori (Renesas Electronics Corporation)
Technical Program Chair: Sheldon Tan (University of California, Riverside)
Technical Program Vice Chair: Masanori Hashimoto (Osaka University, Japan)
Design Contest Co-Chairs: Kousuke Miyaji (Shinshu University, Japan); Akira Tsuchiya (The University of Shiga Prefecture, Japan)

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Call for Papers
The 29th International Workshop on Logic & Synthesis - IWLS 2020
July 18 - 19, 2020, Moscone Center, San Francisco, CA
(co-located with IEEE/ACM Design Automation Conference)

Website: http://www.iwls.org
Paper abstract submission: April 17, 2020
Full paper submission: April 24, 2020
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The International Workshop on Logic & Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

===== Important Dates =====
Paper abstract submission: April 17, 2020
Full paper submission: April 24, 2020
Notification of acceptance: June 5, 2020
Final version due: July 3, 2020

===== Paper submission =====
Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

The submission system is available at http://www.iwls.org

===== Programming Contest =====
The IWLS 2020 edition will also have a programming contest. More information will be available at http://www.iwls.org.

===== Contact =====
General Chair:  Pierre-Emmanuel Gaillardon, University of Utah, USA
Program Chairs: Luca Amaru / Heinz Riener, Synopsys, USA / EPFL, Switzerland
Programming Contest Chair: Gai Liu, Xilinx Inc, USA
Special Session Chair: Tsung-Yi Ho, NTHU, Taiwan
Finance Chair: Cunxi Yu, University of Utah, USA
Proceedings Chair: Zhufei Chu, Ningbo University, China
Publicity Chair: Tsung-Wei Huang, University of Utah, USA
Local Chair: Vinicius Callegaro, Mentor, a Siemens Business, USA

===== Program Committee =====

Luca Amaru                    Synopsys, USA
Anna Bernasconi               University of Pisa, Italy
Vinicius Callegaro            Mentor, a Siemens business, USA
Kai-Hui Chang                 Avery Design Systems, USA
Mihir Choudhury               IBM T. J. Watson, USA
Zhufei Chu                    Ningbo University, China
Sabya Das                     Synopsys, USA
Rolf Drechsler                University of Bremen, Germany
Elena Dubrova                 KTH, Sweden
Stephen Edwards               Columbia University, USA
Petr Fiser                    CTU, Czech Republic
Masahiro Fujita               University of Tokyo, Japan
Pierre-Emmanuel Gaillardon    University of Utah, USA
Tsung-Yi Ho                   NTHU, Taiwan
Tsung-Wei Huang               University of Utah, USA
Paolo Ienne                   EPFL, Switzerland
Hui-Ru Iris Jiang             National Taiwan University, Taiwan
Jie-Hong Roland Jiang         National Taiwan University, Taiwan
Victor Kravets                IBM T. J. Watson, USA
Gai Liu                       Xilinx Inc, USA
Felipe Marranghello           Synopsys, USA
Mayler Martins                Mentor, a Siemens business, USA
Jody Matos                    Silvaco, USA
Alan Mishchenko               UC Berkeley, USA
Augusto Neutzling             Cadence, UK
Vinicius Possani              Synopsys, USA
Madhura Purnaprajna           Amrita University, India
Weikang Qian                  Shanghai Jiao Tong U., China
Andre Inacio Reis             UFRGS, Brazil
Heinz Riener                  EPFL, Switzerland
Tsutomu Sasao                 Meiji University, Japan
Mathias Soeken                Microsoft, USA
Dirk Stroobandt               Ghent University, Belgium
Tiziano Villa                 Universita'' di Verona, Italy
Robert Wille                  Johannes Kepler U., Austria
Cunxi Yu                      University of Utah, USA
Zhiru Zhang                   Cornell University, USA

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